supertex inc. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com HV738 features ? hvcmos technology for high performance ? high density integration ultrasound transmitter ? 0 to 65v output voltage ? 750ma source and sink current in pulse mode ? 110ma source and sink current in cw mode ? up to 20mhz operating frequency ? matched delay times ? 1.2 to 5.0v cmos logic interface ? built-in output drain bleed resistors application ? portable medical ultrasound imaging ? piezoelectric transducer drivers ? ndt ultrasound transmission ? pulse waveform generator general description the supertex HV738 is a four-channel, monolithic, high voltage, high speed pulse generator. it is designed for portable medical ultrasound applications. this high voltage and high speed integrated circuit can also be used for piezoelectric, capacitive or mems sensing in ultrasonic nondestructive detection and sonar ranger applications. the HV738 consists of a controller logic interface circuit, level translators, mosfet gate drivers and high power p-channel and n-channel mosfets as the output stage for each channel. the output stages of each channel are designed to provide peak output currents over 1.1a for pulsing, when in mode 4, with up to 65 volt swings. when in mode 1, all the output stages drop the peak current to 140ma for low-voltage cw mode operation to decrease the power consumption of the ic. the p and n type of power fets gate drivers are supplied by two loating 8.0vdc power supplies referenced to vpp and vnn. this direct coupling topology of the gate drivers not only eliminates two high voltage capacitors per channel, but also makes the pcb layout easier. typical application circuit four-channel, high speed, 65v 750ma ultrasound pulser nin1 sub +8.0v +1.5 to 2.5v logic 0 to +65v en mc1 c1 0 to -65v txn1 1 of 4 channels c2 c3 c5 c4 txp1 x1 d1 d2 +1.5 to 2.5v +65v c6 c7 en_pwr mc0 otp pin1 rgnd rgnd HV738 p-driver n-driver level translator level translator vpp -8.0v vpf vdd gref vpp vnn v nn +8v hv out 1 vnf vsub vll vss r p1 r n1 downloaded from: http:///
2 HV738 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com ordering information device 48-lead qfn 7.00x7.00mm body 1.00mm height (max) 0.50mm pitch HV738 HV738k6-g -g indicates package is rohs compliant (green)absolute maximum ratings parameter value v ss , power supply reference 0v v ll , positive logic supply -0.5v to +7v v dd , positive logic and level translator supply -0.5v to +14v (v pp -v pf ) positive loating gate drive supply -0.5v to +14v (v nf - v nn ) negative gate loating drive supply -0.5v to +14v (v pp -v nn ) differential high voltage supply +140v v pp , high voltage positive supply -0.5v to +70v v nn , high voltage negative supply +0.5v to -70v otp, over temperature protection output -0.5v to +7v all logic input pin x , nin x and en voltages -0.5v to +7v (v sub - v ss ) substrate to v ss voltage difference +140v (v pp Ctxp x ) v pp to txp x voltage difference +140v (v sub - txp x ) substrate to txp x voltage difference +140v (txn x -v nn ) txn x to v nn voltage difference +140v operating temperature -40c to 125c storage temperature -65c to 150c thermal resistance, ja 29c/w thermal resistance, jc (junction to thermal pad) 0.5c/w absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. power-up sequence step description 1 v sub 2 v ll with logic signal low 3 v dd 4 (v pp -v pf ) and (v nf Cv nn ) 5 v pp and v nn 6 logic control signals power-down sequence step description 1 all logic signals go to low 2 v pp and v nn 3 (v pp -v pf ) and (v nf Cv nn ) 4 v dd 5 v ll 6 v sub pin conigurationpackage marking 1 48 l = lot number yy = year sealed ww = week sealed a = assembler id c = country of origin = green packagin g HV738k6 lllllllll yyww aaa ccc 48-lead qfn 48-lead qfn (top view) package may or may not include the following marks: si or downloaded from: http:///
3 HV738 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com operating supply voltages and current (4 channel active) (operating conditions, unless otherwise speciied, v ss = 0v, v ll = +2.5v, v dd = +8v, v pp -v pf = +8v, v nn -v nf = -8v, v pp =+65v, v nn = -65v, t a = 25c) sym parameter min typ max units conditions v ll logic voltage reference 1.2 2.5 5.0 v --- v dd internal voltage supply 7.5 8.0 10 v --- v pf positive gate driver supply (v pp -10) (v pp -8.0) (v pp -7.5) v floating driver voltage supplies. v nf negative gate drive supply (v nn +7.5) (v nn +8.0) (v nn +10) v v sub ic substrate voltage v dd v pp +65 v must be the most positive potential of the ic. v pp positive hv supply 0 - +65 v --- v nn negative hv supply -65 - 0 v --- sr max slew rate limit of v pp , v nn - - 25 v/s built-in slew rate detection protec- tion. i ll v ll current en = low - 35 120 a --- i ddq v dd current en = low - 10 - a --- i dden v dd current en = high - 0.75 2.0 ma f = 0mhz i dden v dd current mode = 4 - 2.0 - ma f = 5.0mhz, continuous, no loads i ddencw v dd current mode = 1 - 5.0 - ma i ppq v pp current en = low - 10 20 a f = 0mhz i ppen v pp current mode = 4 - 200 - ma f = 5.0mhz, continuous, no loads i ppencw v pp current mode = 1 - 140 - ma i nnq v nn current en = low - 10 20 a f = 0mhz i nnen v nn current mode = 4 - 170 - ma f = 5.0mhz, continuous, no loads i nnencw v nn current mode = 1 - 140 - ma i pfq v pf current en = low - 8.0 20 a f = 0mhz i pfen v pf current mode = 4 - 30 - ma f = 5.0mhz, continuous, no loads i pfencw v pf current mode = 1 - 10 - ma i nfq v nf current en = low - 10 20 a f = 0mhz i nfen v nf current mode = 4 - 12 - ma f = 5.0mhz, continuous, no loads i nfencw v nf current mode = 1 - 5.0 - ma under voltage and over temperature protection sym parameter min typ max units conditions v pull_up open drain pull-up voltage - - 5.0 v --- v uvdd v dd threshold 3.5 - 6.5 v --- v uvll v ll threshold 0.7 - 1.0 v --- v uvvf v pf , v nf threshold 3.5 - 6.5 v --- v ol_otp otp lag output low voltage - - 1.0 v v ll = 2.5v, otp = active, i pull_up = 1.0ma. i otp max. open drain outputcurrent - 1.0 - ma --- t otp over temperature threshold 95 110 125 c if over temperature occurred, otp low and all tx outputs will be hiz. t hys otp output reset hysteresis - 7.0 - downloaded from: http:///
4 HV738 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com dc electrical characteristics(operating conditions, unless otherwise speciied, v ss = 0v, v ll = +2.5v, v dd = +8v, v pp -v pf = +8v, v nn -v nf = -8v, v pp = +65v, v nn = -65v,t a = 25c) output p-channel mosfet, txp (mode 4) sym parameter min typ max units conditions i out output saturation current 0.75 1.2 - a --- r on channel resistance - 13 - i sd = 100ma c oss output capacitance - 50* - pf v ds = 25v, f = 1.0mhz output n-channel mosfet, txn (mode 4) sym parameter min typ max units conditions i out output saturation current 0.75 1.1 - a --- r on channel resistance - 12.5 - i sd = 100ma c oss output capacitance - 20* - pf v ds = 25v, f = 1.0mhz mosfet drain bleed resistor sym parameter min typ max units conditions r p/n1~4 output bleed resistance 10 20 30 k --- p ro bleed resistors power limit - - 40 mw --- logic inputs sym parameter min typ max units conditions v ih input logic high voltage (v ll -0.4) - v ll v --- v il input logic low voltage 0 - 0.4 v --- i ih input logic high current - - 10 a --- i il input logic low current -10 - - a --- c in input logic capacitance - - 5.0* pf --- ac electrical characteristics(operating conditions, unless otherwise speciied, v ss = 0v, v ll = +2.5v, v dd = +8v, v pp - v pf = +8v, v nn - v nf = -8v, v pp = +65v, v nn = -65v, t a = 25c) sym parameter min typ max units conditions t r output rise time - 35 - ns 330pf//2.5k load t f output fall time - 43 - ns f out output frequency range - - 20 mhz 100 resistor load hd2 second harmonic distortion - -35* - db t en enable time - 180 500 s t dis disable time - 2.8 10 s t dr delay time on inputs rise - 22 - ns 7.5 resistor load(see timing diagram) t df delay time on inputs fall - 22 - ns t delay delay time matching - 3.0 - ns p to n, channel to channel t dm delay on mode change - 2.5 10 s 100 resistor load t j delay jitter on rise or fall - 13* - ps v pp /v nn = 25v, input t r 50% to hv out t r or t f 50%, with 330pf//2.5k load * guaranteed by design. downloaded from: http:///
5 HV738 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com 10% 90% pinx nin x output v nn v pp t r 10% t r 90% 0 50% 50% t dr t df switch ac test timing diagram t drp 50% pinx nin x t dfp txpx i out 0a txnx 50% 50% 50% nin 1 sub v pf v dd g ref en mc1 txn1 v nf 1of n channels txp1 r1 r2 v ll en_pwr mc0 otp v ss pin1 rgnd r p1 r n1 rgnd v pp v nn 0a v sub p-drivern-driver level translator level translator t drn t dfn i out downloaded from: http:///
6 HV738 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com pin # name function 1 vdd positive internal voltage supply (+8.0v). 2 vss power supply return (0v). 3 pin1 input logic control of high voltage output p-fet of channel 1, hi = on, low = off. 4 nin1 input logic control of high voltage output n-fet of channel 1, hi = on, low = off. 5 pin2 input logic control of high voltage output p-fet of channel 2, hi = on, low = off. 6 nin2 input logic control of high voltage output n-fet of channel 2, hi = on, low = off. 7 pin3 input logic control of high voltage output p-fet of channel 3, hi = on, low = off. 8 nin3 input logic control of high voltage output n-fet of channel 3, hi = on, low = off. 9 pin4 input logic control of high voltage output p-fet of channel 4, hi = on, low = off. 10 nin4 input logic control of high voltage output n-fet of channel 4, hi = on, low = off. 11 vss power supply return (0v). 12 vdd positive internal voltage supply (+8.0v). 13 otp over temperature protection output, open n-fet drain, active low if ic temperature >110c. 14 mc1 output current mode control pins, see drive mode control table. 15 mc0 16 thermal pad (vsub) substrate of the ic, substrate bottom is internally connected to the central thermal pad on the bottom of package. it must be connected to vsub, the most positive potential of the ic externally. 17 vpf p-fet drive loating power supply, (v pp - v pf ) = +8.0v. pin description truth table (all modes) logic inputs output en pin x nin x txp x txn x 1 0 0 off off 1 1 0 on off 1 0 1 off on 1 1 1 on ? on ? 0 x x off off ? not allowed, may damage ic. drive mode control table mode mc1 mc0 i sc (a) r onp () r onr () 1 0 0 0.28 56.0 54.0 2 0 1 0.38 41.0 39.5 3 1 0 0.65 24.0 23.0 4 1 1 1.20 13.0 12.5 notes: 1. v pp /v nn = +/-65v, v dd = (v pp C v pf ) = (v nf C v nn ) = +8.0v 2. i sc is current into 1.0 to gnd 3. r on calculated from v out into 100 load downloaded from: http:///
7 HV738 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com pin # name function 18 vpp positive high voltage power supply (+65v). 1920 21 vnn negative high voltage power supply (-65v). 2223 24 vnf n-fet drive loating power supply, (v nf - v nn ) = +8.0v. 25 thermal pad (vsub) substrate of the ic, substrate bottom is internally connected to the central thermal pad on the bottom of package. it must be connected to vsub, the most positive potential of the ic externally. 26 rgnd bleed resistors common return ground. (both pins must be used) 27 txn4 output n-fet drain (open drain output) for channel 4. 28 txp4 output p-fet drain (open drain output) for channel 4. 29 txn3 output n-fet drain (open drain output) for channel 3. 30 txp3 output p-fet drain (open drain output) for channel 3. 31 txn2 output n-fet drain (open drain output) for channel 2. 32 txp2 output p-fet drain (open drain output) for channel 2. 33 txn1 output n-fet drain (open drain output) for channel 1. 34 txp1 output p-fet drain (open drain output) for channel 1. 35 rgnd bleed resistors common return ground. (both pins must be used) 36 thermal pad (vsub) substrate of the ic, substrate bottom is internally connected to the central thermal pad on the bottom of package. it must be connected to vsu b , the most positive potential of the ic externally. 37 vnf n-fet drive loating power supply, (v nf - v nn ) = +8.0v. 38 vnn negative high voltage power supply (-65v). 3940 41 vpp positive high voltage power supply (+65v). 4243 44 vpf p-fet drive loating power supply, (v pp - v pf ) = +8.0v. 45 thermal pad (vsub) substrate of the ic, substrate bottom is internally connected to the central thermal pad on the bottom of package. it must be connected to vsub, the most positive potential of the ic externally. 46 en chip power enable hi = on, low = off. 47 gref logic low reference, logic ground (0v). 48 vll logic hi voltage reference input (+2.5v). pin description (cont.) downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. supertex inc . does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//www .supertex.com) ?2011 supertex inc. a ll rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com 8 HV738 (the package drawing(s) in this data sheet may not relect the most current speciications. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-HV738c041309 48-lead qfn package outline (k6) 7.00x7.00mm body, 1.00mm height (max), 0.50mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.80 0.00 0.20 ref 0.18 6.85* 1.25 6.85* 1.25 0.50 bsc 0.30 ? 0.00 0 o nom 0.90 0.02 0.25 7.00 - 7.00 - 0.40 ? - - max 1.00 0.05 0.30 7.15* 5.45 7.15* 5.45 0.50 ? 0.15 14 o jedec registration mo-220, variation vkkd-6, issue k, june 2006. * this dimension is not speciied in the jedec drawing. ? this dimension differs from the jedec drawing. drawings are not to scale. supertex doc.#: dspd-48qfnk67x7p050, version c041009. notes: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. 2. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. 3. the inner tip of the lead may be either rounded or square. seating plane to p v iew side view bottom view a a1 d e d2 b e2 a3 l l1 vi ew b vi ew b 1 note 3 note 2 note 1(index area d/2 x e/2) note 1(index area d/2 x e/2) e 48 1 48 downloaded from: http:///
|
